Write back : Write operations are usually made only to the cache.If there is no cache coherence policy in-place, the wrong data would be read and invalid results would be produced, possibly crashing the program. To trigger the cache invalidation we need cache coherence policies. This cache miss forces the second core’s cache entry to be updated. When the second core attempts to read that value from its cache, it will not have the most recent version unless its cache entry is invalidated and a cache miss occurs.
PRIVATE CACHE PROGRAM UPDATE
Imagine a scenario where multiple copies of same data exists in different caches simultaneously, and if the processors are allowed to update their own copies freely, an inconsistent view of memory can result.įor example, imagine a dual-core processor where each core brought a block of memory into its private cache, and then one core writes a value to a specific location. The Cache Coherence Problem is the challenge of keeping multiple local caches synchronized when one of the processors updates its local copy of data which is shared among multiple caches. Each core has its own L1 and L2 caches and they need to always be in-sync with each other to have the most up-to-date version of the data. Cache coherence is a concern raised in a multi-core system distributed L1 and L2 caches.
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